System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions

ABSTRACT

Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

CROSS REFERENCE TO RELATED APPLICATIONS

This patent application is a continuation of co-pending U.S. patentapplication Ser. No. 15/232,551, filed Aug. 9, 2016, which is acontinuation of U.S. patent application Ser. No. 13/691,218, filed Nov.30, 2012, now U.S. Issued U.S. Pat. No. 9,411,739, Issued on Aug. 9,2016, all of which are hereby incorporated by reference in theirentirety into this application.

BACKGROUND

A natural implementation of transactional memory is to require an oldertransaction to commit before retiring instructions that are part of ayounger transaction. However, in an out-of-order processor it is oftenthe case that a significant number of operations in a youngertransaction have finished executing while waiting for the oldertransaction to commit. For example, a single store in the oldertransaction may require hundreds of cycles waiting for memory torespond. In the interim, an out-of-order machine could have executed allthe instructions in a younger transaction. When the older transactionfinally commits, there is now a backlog of instructions to retire fromthe younger transaction.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

FIG. 1 illustrates a block diagram of portions of a processor core 100,according to an embodiment of the invention.

FIG. 2 illustrates an embodiment of a Copy-on-Write (COW) buffer.

FIG. 3 illustrates an embodiment of a data cache that allows for markingof memory state.

FIG. 4 illustrates an exemplary ROB.

FIG. 5 illustrates an embodiment of using TM region indicators for loadinstructions.

FIG. 6 illustrates an embodiment of using TM region indicators for storeinstructions.

FIG. 7 illustrates an embodiment of using TM region indicators forarithmetic instructions.

FIG. 8 is a block diagram of a register architecture 800 according toone embodiment of the invention.

FIG. 9A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the invention.

FIG. 9B is a block diagram illustrating both an exemplary embodiment ofan in-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the invention.

FIGS. 10A-B illustrate a block diagram of a more specific exemplaryin-order core architecture, which core would be one of several logicblocks (including other cores of the same type and/or different types)in a chip.

FIG. 11 is a block diagram of a processor 1100 that may have more thanone core, may have an integrated memory controller, and may haveintegrated graphics according to embodiments of the invention.

FIGS. 12-15 are block diagrams of exemplary computer architectures.

FIG. 16 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth.However, it is understood that embodiments of the invention may bepracticed without these specific details. In other instances, well-knowncircuits, structures and techniques have not been shown in detail inorder not to obscure the understanding of this description.

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

Exemplary Processor Core

FIG. 1 illustrates a block diagram of portions of a processor core 100,according to an embodiment of the invention. In one embodiment, thearrows shown in FIG. 1 illustrate the flow of instructions through thecore 100. One or more processor cores (such as the processor core 100)may be implemented on a single integrated circuit chip (or die) such asdiscussed with reference to FIG. 1. Moreover, the chip may include oneor more shared and/or private caches (e.g., cache), interconnections,memory controllers, or other components. In an embodiment, the processorcore 100 shown in FIG. 1 may be utilized to execute one or more types ofthreads including those that correspond to a virtualized transactionmode, a non-virtualized (or restricted) transaction mode, and anon-transaction mode.

As illustrated in FIG. 1, the processor core 100 may include a fetchunit 102 to fetch instructions from an instruction cache 101 forexecution by the core 100. The instructions may be fetched from L1instruction cache 101 or any storage device such as memory 164 and/orthe memory devices. The core 100 may also include a decode unit 104 todecode the fetched instruction. For instance, the decode unit 104 maydecode the fetched instruction into a plurality of uops(micro-operations). Additionally, the core 100 may include a scheduleunit 106. The schedule unit 106 may perform various operationsassociated with storing decoded instructions (e.g., received from thedecode unit 104) until the instructions are ready for dispatch, e.g.,until all source values of a decoded instruction become available. Inone embodiment, the schedule unit 106 may schedule and/or issue (ordispatch) decoded instructions to an execution unit 108 for execution.The execution unit 108 may execute the dispatched instructions afterthey are decoded (e.g., by the decode unit 104) and dispatched (e.g., bythe schedule unit 106). In an embodiment, the execution unit 108 mayinclude more than one execution unit, such as a memory execution unit,an integer execution unit, a floating-point execution unit, or otherexecution units. Further, the execution unit 108 may executeinstructions out-of-order. Hence, the processor core 100 may be anout-of-order processor core in one embodiment. The core 100 may alsoinclude a retirement unit 110. The retirement unit 110 may retireexecuted instructions after they are committed. In an embodiment,retirement of the executed instructions may result in processor statebeing committed from the execution of the instructions, physicalregisters used by the instructions being de-allocated, etc.

As illustrated in FIG. 1, the core 100 may additionally include a tracecache or microcode read-only memory (uROM) 111 to store microcode and/ortraces of instructions that have been fetched (e.g., by the fetch unit102). The microcode stored in the uROM 111 may be used to configurevarious hardware components of the core 100. In an embodiment, themicrocode stored in the uROM 111 may be loaded from another component incommunication with the processor core 100, such as a computer-readablemedium or other storage device discussed. The core 100 may also includea reorder buffer (ROB) 112 to store information about in flightinstructions (or uops) for access by various components of the processorcore 100. The core 100 may further include a RAT (register alias table)114 to maintain a mapping of logical (or architectural) registers (suchas those identified by operands of software instructions) tocorresponding physical registers. In one embodiment, each entry in theRAT 114 may include a ROB identifier assigned to each physical register.Additionally, a load buffer 116 and a store buffer 118 (which may bereferred to collectively herein as memory order buffer (MOB)) may storepending memory operations that have not loaded or written back to a mainmemory (e.g., a memory that is external to the processor core 100, suchas memory 164), respectively. A MOB logic 119 may perform variousoperations relating to the buffers 116 and 118 such as discussed herein.Furthermore, the processor core 100 may include a bus unit 120 to allowcommunication between components of the processor core 100 and othercomponents via one or more buses. One or more fill buffers 122 maytemporary store data that is received (e.g., over the buses) from thememory 164 prior to storing the received data into the cache 162.

In one embodiment, one or more transaction status registers 160 may beincluded in the core 100. Each transaction status register 160 maycorrespond to a transaction that is executing on the core 100. A firsttransaction may store a value in the transaction status register 160 ofa second transaction to indicate that the second transaction is to abort(e.g., due to a higher priority assigned to the first transaction thanthe second transaction, for example, to avoid conflicts). In anembodiment, each transaction may monitor its respective status register160 to determine whether it should abort. For example, the statusregister 160 may be used to abort a transaction even in situations wherethe transaction may be suspended, e.g., switched out of the core (100)temporarily. This may allow other transactions to proceed without havingto wait for an explicit abort. Also, the status registers 160 may beimplemented in memory (e.g., within the cache 162 and/or memory 164),instead of a hardware register.

The following discussion with detail embodiments of techniques forimproving TM throughput using a TM region indicator (or color). Theinitial discussion will discuss at a high-level the use of TM regionindictors and various components that are typically utilized inimproving throughput. More specific examples of handling loads andstores of a transaction are detailed after that.

Region Indication

Multiple transactional memory routines from the same thread may run on aprocessor at a given point in time and are ordered one after the other.These routines are called “regions” in throughout this description. Inan embodiment, transactions are delineated by begin and end instructions(for example, XBEGIN and XEND). As detailed herein, a TM regionindicator is used to distinguish instructions that come from one TMregion from those coming from another TM region. This indicator may beassigned to an instruction (either a macro instruction ormicrooperation) dynamically at many different points in a pipeline orstatically prior to runtime. The allocate stage of a pipeline is onepoint before out-of-order execution at which instructions are still seenin order and therefore would provide an opportune time to tag aninstruction with its TM region indicator. During this stage, a decisionis made as to what storage location is to be used (such as a position inthe load or store buffer of a MOB), an assignment of a physical registerfor use by the instruction (this may include register renaming), andwhich functional unit to use (if necessary). However, other stages suchas fetch, decode, etc. may be also utilized. Regardless of which stageis used for TM region indicator tagging, TM region indicator informationis placed into the reordering buffer (ROB) 112.

An example of TM region indicating using “n” as the number ofconsecutive transactional memory regions from which instructions areallowed to retire is detailed herein. For example, when n=3 instructionsfrom the first TM region are assigned color 0; the next region'sinstructions are assigned color 1; the next region color 2; and the nextregion color 0; and so forth. As such, the TM region indicationassignment stage (such as allocate) does not block instructions or TMs,but simply assigns TM region colors in a round-robin fashion. For timingreasons, an implementation may choose to duplicate the color informationelsewhere in the pipeline. For example, load buffer entries may betagged with their color to facilitate setting the correct (associated)read-bit (R-bit) in the data-cache (D-cache), etc. as will be discussedlater.

Checkpointing for Rollback

TM requires a method for checkpointing registers so that register statemay be restored in the event that a transaction is aborted. In aprocessor in which architectural registers are renamed to physicalregisters, this can be done by retaining the pre-transactional value ofan architectural register in its physical register and assigning a newphysical register to an instruction within the TM region that overwritesit. Typically, a transaction cannot free physical registers for use byother instructions including those within other transactions. Thestructure that maintains the mapping from checkpointed architecturalregisters to physical registers is called the copy-on-write (COW)buffer. In some embodiments, the COW is a part of the retirement unit110.

In order to support the ability to maintain multiple registercheckpoints the COW structure may be used with the addition ofintermediate pointers marking the separations between TM regions. Anexemplary COW is illustrated in FIG. 2. As shown, a COW stores registersfor instructions that have retired (in chronological order), but are notyet committed.

Using the previous n=3 example, there are three TM regions within theillustrated COW. Pointers are shown in the figure and these pointersdelineate the TM regions. A first pointer, E0, identifies the positionof the last committed instruction in the COW. Note that there are someregisters that have been committed, but are not yet deallocated for useby the processor. These registers may be reclaimed at any time.

A second pointer, E1, identifies the boundary between the oldest TMregion and the next older TM region. Between the first and secondpointers are instructions that have retired, but are not committed forthe oldest TM region.

A third pointer, E2, identifies the boundary between the youngest regionand the currently retiring position. Between the third and secondpointers are instructions that have retired, but are not committed for amiddle TM region. Instructions that have retired, but have not yetreached pointer E2 are from the youngest TM region. Each of the abovepointers may be stored within the COW itself or stored in one or morededicated registers.

The currently retiring instruction has its own pointer, the retirementpointer. When the oldest region commits (or is deemed to beuncommittable), E0 is updated to point to the E1 position, E1 is updatedto point to the E2 position, and E2 is updated to point to theretirement pointer. Then, the retirement pointer may advance into thenext TM region, etc.

Data Cache

TM requires a method for marking memory state that has beenspeculatively read so that changes to the state by other executionthreads can be detected. These changes by other threads would violatethe atomicity of the transaction and so it is necessary to abort thetransaction if they occur.

FIG. 3 illustrates an embodiment of a data cache (such as data cache162) that allows for marking of memory state. In this embodiment,marking is accomplished by adding a single bit per cache line which iscalled the read-bit (R-bit). The R-bit may be stored in the cache itselfor as a separate data structure. When data is speculatively read fromthe cache line the R-bit is set for that cache line. When thetransaction is completed (either by a commit or by an abort) R-bits arecleared.

To support the ability to maintain multiple read-sets (each read set isthe set of cache lines read within), a R-bit is provided for eachconsecutive region from which retirement has been allowed. This is doneso that loads from different TM regions may both set their correspondingread-bits without having to stall until the older TM regions commit.

For example, in the n=3 example, there are 3 R-bits, one associated witheach color. When a load retires, the R-bit associated with the load'scolor is marked in the data-cache. When a transaction of a given colorcommits, the R-bits for that color are cleared. When a transaction of agiven color aborts, the R-bits for its color and the R-bits for thecolors of any younger transactions are cleared. This is because anaborted transaction implies that all younger transactions must also beaborted.

TM also requires a method for checkpointing memory state so thatpre-transactional memory values may be restored in the event that atransaction is aborted. A method to do this involves writing speculativedata to the first-level data cache (such as data cache 162) andpreventing other execution threads from seeing the speculative data.After a transaction commits the speculative data is made globallyvisible. On the other hand, should the transaction abort, thespeculative data is discarded since the pre-transactionalarchitecturally committed memory values are in lower levels of the cachehierarchy. In order to distinguish cache lines containing speculativedata, one bit is added to each data cache line to indicate that the linecontains speculatively written data, the write bit (W-bit). Speculativedata is written to the cache only after the store instruction is retired(these are known as senior stores). The store's data is maintained in astore buffer (such as in a MOB) prior to its being written to the datacache. Since data is maintained in the store buffer in program order, itis not necessary to add additional W-bits to the data cache. Instead,senior store processing (reading data out of the store buffer for theoldest retired store, writing it to the data cache and setting theW-bit, and removing the entry from the store buffer) may be used suchthat it only proceeds for the oldest TM region. When the last store ofthe oldest TM region is processed, senior store processing is halteduntil the oldest TM region commits. When the region commits, thespeculative stores are no longer speculative, and hence are madeglobally visible. The W bits are cleared, and senior stores from thenext TM region (which is now the oldest TM region) can begin processing.

Retirement from ROB

Retirement can now be relaxed such that instructions from “n” TM regionsmay be retired before having to wait until the oldest TM region iscommitted. As seen in FIG. 4, more than n TM regions may be present inthe ROB at one time. The instructions from these regions have beenassigned to one of n colors as detailed above. Retirement may retire theoldest 15 instructions in this example (5 from each of the threeregions) instead of having to wait on a per region basis. Retirementstalls before retiring the first instruction of the oldest TM regionthat is not in an initial grouping from that TM region until the oldestTM region has committed. In this example, the 16th instruction has beenassigned the same color as the TM region that is waiting to commit andwill be blocked from retirement.

Exemplary Method for Load Instruction Processing of a Transaction

FIG. 5 illustrates an embodiment of using TM region indicators for loadinstructions. At 501, a transaction memory region indicator is assignedto a load instruction of that transaction. As noted before, this mayoccur during an allocation stage of a pipeline by allocation orallocation/rename logic. Additionally, as noted previously, transactionstypically begin with a predetermined instruction (such as XBEGIN) andend with a predetermined instruction (such as XEND). This description isfrom the point of view of a single load instruction, however, it shouldbe understood that each instruction of the transaction would have aregion indicator assigned to it.

The previous physical register(s) associated with the instruction thatwere written into are copied into the COW at 503. For example, for theinstruction LOAD RAX, (memory location) where RAX had been previouslymapped to physical register 17, physical register 17 is stored in theCOW and an allocate pointer (described above) is placed into a pointerstorage location. Note that the previous mapping of RAX (physicalregister 17) is stored in the COW because it contains the architecturalvalue of RAX that had been written prior to this TM region. So, if theTM region were to abort, the value for RAX can be properly restored. Ifmultiple instructions within the same TM region all write to RAX, onlythe first of these needs to preserve the previous mapping in the COW.

The instruction is executed at 505. Of course, because this is anout-of-order machine, other transactions may be following this samecourse of action.

The load instruction is retired (for example from the ROB) at 507. Asnoted above, retirement may occur without having to wait for until theoldest TM region is committed.

A read-bit is set for the load that has been retired into acorresponding data cache entry at 509. This read-bit corresponds to thecolor or region indicator that was assigned at 501.

At some later point, a decision is made of whether or not to commit thetransaction at 511. Typically, this decision is reached when an XENDinstruction is received and processed, and nothing has caused an abortof the transaction. If the transaction is allowed to commit, the R-bitsassociated with that transaction are cleared and the physical registersassociated with the transaction are allowed to be freed from the COW foruse by the processor and so the pointers of the COW are movedaccordingly at 515. If the transaction is to be aborted, then the stateis rolled-back to what it was before the transaction by using the storedregisters in the COW at 513. An abort may be caused, for example, byanother thread having modified data that has been speculatively loaded.These registers are also free to be used by the processor. The read-bitsare also cleared in preparation for a possible future transaction.

Exemplary Method for Store Instruction Processing of a Transaction

FIG. 6 illustrates an embodiment of using TM region indicators for storeinstructions. At 601, a transaction memory region indicator is assignedto a store instruction of that transaction. As noted before, this mayoccur during an allocation stage of a pipeline by allocation orallocation/rename logic. Additionally, as noted previously, transactionstypically begin with a predetermined instruction (such as XBEGIN) andend with a predetermined instruction (such as XEND). This description isfrom the point of view of a single store instruction, however, it shouldbe understood that each instruction of the transaction would have aregion indicator assigned to it.

The store instruction of the transaction is executed at 605. Of course,because this is an out-of-order machine, other transactions may befollowing this same course of action. At this stage, the instructionsare also placed into a store buffer of a MOB if such a mechanism is usedin the processor.

The store instruction is retired (for example from the ROB) at 607 forthe oldest TM region. As noted above, senior store processing is usedfor retirement of the oldest TM region by reading data out of the storebuffer for the oldest retired store, writing it to the data cache andsetting the W-bit, and removing the entry from the store buffer.

A write-bit is written for the store that has been retired into acorresponding data cache entry at 609.

At some later point, a decision is made of whether or not to commit thetransaction at 611. Typically, this decision is reached when an XENDinstruction is received and processed, and nothing has caused an abortof the transaction. If the transaction is allowed to commit, the W-bitsassociated with that transaction are cleared, and therefore the storesassociated with the transaction that had been speculatively written intothe data cache are now committed and hence are made globally visible.Once the oldest TM region commits the next oldest TM region may retireaccording to senior store processing. If the transaction is to beaborted, then the state is rolled-back to what it was before thetransaction began. This is done by invalidating all the entries in thedata cache that had been speculatively written (as indicated by thewrite bit having been set for that cache line). The write bits are alsocleared in preparation for a possible future transaction. If thetransaction is aborted, all in-progress younger transactions are alsoaborted.

While the above methods have been described as being separate load andstore processing, transactions will virtually always have loads andstores. As such, the aspects of the proceeding figures may be mixedtogether.

Exemplary Method for Arithmetic Instruction Processing of a Transaction

FIG. 7 illustrates an embodiment of using TM region indicators forarithmetic instructions. At 701, a transaction memory region indicatoris assigned to a arithmetic instruction of that transaction. As notedbefore, this may occur during an allocation stage of a pipeline byallocation or allocation/rename logic. Additionally, as notedpreviously, transactions typically begin with a predeterminedinstruction (such as XBEGIN) and end with a predetermined instruction(such as XEND). This description is from the point of view of a singleload instruction, however, it should be understood that each instructionof the transaction would have a region indicator assigned to it.

The previous physical register(s) associated with the instruction thatwere written into are copied into the COW at 703. For example, for theinstruction ADD RAX, RAX where RAX had been previously mapped tophysical register 17, physical register 17 is stored in the COW and anallocate pointer (described above) is placed into a pointer storagelocation. Note that the previous mapping of RAX (physical register 17)is stored in the COW because it contains the architectural value of RAXthat had been written prior to this TM region. So, if the TM region wereto abort, the value for RAX can be properly restored. If multipleinstructions within the same TM region all write to RAX, only the firstof these needs to preserve the previous mapping in the COW.

The instruction is executed at 705.

The arithmetic instruction is retired (for example from the ROB) at 707.As noted above, retirement may occur without having to wait for untilthe oldest TM region is committed.

At some later point, a decision is made of whether or not to commit thetransaction at 711. Typically, this decision is reached when an XENDinstruction is received and processed, and nothing has caused an abortof the transaction. If the transaction is allowed to commit, thephysical registers associated with the transaction are allowed to befreed from the COW for use by the processor and so the pointers of theCOW are moved accordingly at 715. If the transaction is to be aborted,then the state is rolled-back to what it was before the transaction byusing the stored registers in the COW at 713. An abort may be caused,for example, by another thread having modified data that has beenspeculatively loaded. These registers are also free to be used by theprocessor.

Exemplary Register Architecture

FIG. 8 is a block diagram of a register architecture 800 according toone embodiment of the invention. In the embodiment illustrated, thereare 32 vector registers 810 that are 512 bits wide; these registers arereferenced as zmm0 through zmm31. The lower order 256 bits of the lower16 zmm registers are overlaid on registers ymm0-16. The lower order 128bits of the lower 16 zmm registers (the lower order 128 bits of the ymmregisters) are overlaid on registers xmm0-15. Write mask registers 815are referenced as k0-7.

General-purpose registers 825—in the embodiment illustrated, there aresixteen 64-bit general-purpose registers that are used along with theexisting x86 addressing modes to address memory operands. Theseregisters are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI,RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) 845, on which isaliased the MMX packed integer flat register file 850—in the embodimentillustrated, the x87 stack is an eight-element stack used to performscalar floating-point operations on 32/64/80-bit floating point datausing the x87 instruction set extension; while the MMX registers areused to perform operations on 64-bit packed integer data, as well as tohold operands for some operations performed between the MMX and XMMregisters.

Alternative embodiments of the invention may use wider or narrowerregisters. Additionally, alternative embodiments of the invention mayuse more, less, or different register files and registers.

Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for differentpurposes, and in different processors. For instance, implementations ofsuch cores may include: 1) a general purpose in-order core intended forgeneral-purpose computing; 2) a high performance general purposeout-of-order core intended for general-purpose computing; 3) a specialpurpose core intended primarily for graphics and/or scientific(throughput) computing. Implementations of different processors mayinclude: 1) a CPU including one or more general purpose in-order coresintended for general-purpose computing and/or one or more generalpurpose out-of-order cores intended for general-purpose computing; and2) a coprocessor including one or more special purpose cores intendedprimarily for graphics and/or scientific (throughput). Such differentprocessors lead to different computer system architectures, which mayinclude: 1) the coprocessor on a separate chip from the CPU; 2) thecoprocessor on a separate die in the same package as a CPU; 3) thecoprocessor on the same die as a CPU (in which case, such a coprocessoris sometimes referred to as special purpose logic, such as integratedgraphics and/or scientific (throughput) logic, or as special purposecores); and 4) a system on a chip that may include on the same die thedescribed CPU (sometimes referred to as the application core(s) orapplication processor(s)), the above described coprocessor, andadditional functionality. Exemplary core architectures are describednext, followed by descriptions of exemplary processors and computerarchitectures.

Exemplary Core Architectures In-Order and Out-of-Order Core BlockDiagram

FIG. 9A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the invention. FIG.9B is a block diagram illustrating both an exemplary embodiment of anin-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the invention. The solid linedboxes in FIGS. 9A-B illustrate the in-order pipeline and in-order core,while the optional addition of the dashed lined boxes illustrates theregister renaming, out-of-order issue/execution pipeline and core. Giventhat the in-order aspect is a subset of the out-of-order aspect, theout-of-order aspect will be described.

In FIG. 9A, a processor pipeline 900 includes a fetch stage 902, alength decode stage 904, a decode stage 906, an allocation stage 908, arenaming stage 910, a scheduling (also known as a dispatch or issue)stage 912, a register read/memory read stage 914, an execute stage 916,a write back/memory write stage 918, an exception handling stage 922,and a commit stage 924.

FIG. 9B shows processor core 990 including a front end unit 930 coupledto an execution engine unit 950, and both are coupled to a memory unit970. The core 990 may be a reduced instruction set computing (RISC)core, a complex instruction set computing (CISC) core, a very longinstruction word (VLIW) core, or a hybrid or alternative core type. Asyet another option, the core 990 may be a special-purpose core, such as,for example, a network or communication core, compression engine,coprocessor core, general purpose computing graphics processing unit(GPGPU) core, graphics core, or the like.

The front end unit 930 includes a branch prediction unit 932 coupled toan instruction cache unit 934, which is coupled to an instructiontranslation lookaside buffer (TLB) 936, which is coupled to aninstruction fetch unit 938, which is coupled to a decode unit 940. Thedecode unit 940 (or decoder) may decode instructions, and generate as anoutput one or more micro-operations, micro-code entry points,microinstructions, other instructions, or other control signals, whichare decoded from, or which otherwise reflect, or are derived from, theoriginal instructions. The decode unit 940 may be implemented usingvarious different mechanisms. Examples of suitable mechanisms include,but are not limited to, look-up tables, hardware implementations,programmable logic arrays (PLAs), microcode read only memories (ROMs),etc. In one embodiment, the core 990 includes a microcode ROM or othermedium that stores microcode for certain macroinstructions (e.g., indecode unit 940 or otherwise within the front end unit 930). The decodeunit 940 is coupled to a rename/allocator unit 952 in the executionengine unit 950.

The execution engine unit 950 includes the rename/allocator unit 952coupled to a retirement unit 954 and a set of one or more schedulerunit(s) 956. The scheduler unit(s) 956 represents any number ofdifferent schedulers, including reservations stations, centralinstruction window, etc. The scheduler unit(s) 956 is coupled to thephysical register file(s) unit(s) 958. Each of the physical registerfile(s) units 958 represents one or more physical register files,different ones of which store one or more different data types, such asscalar integer, scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point, status (e.g., aninstruction pointer that is the address of the next instruction to beexecuted), etc. In one embodiment, the physical register file(s) unit958 comprises a vector registers unit and a scalar registers unit. Theseregister units may provide architectural vector registers, vector maskregisters, and general purpose registers. The physical register file(s)unit(s) 958 is overlapped by the retirement unit 954 to illustratevarious ways in which register renaming and out-of-order execution maybe implemented (e.g., using a reorder buffer(s) and a retirementregister file(s); using a future file(s), a history buffer(s), and aretirement register file(s); using a register maps and a pool ofregisters; etc.). The retirement unit 954 and the physical registerfile(s) unit(s) 958 are coupled to the execution cluster(s) 960. Theexecution cluster(s) 960 includes a set of one or more execution units962 and a set of one or more memory access units 964. The executionunits 962 may perform various operations (e.g., shifts, addition,subtraction, multiplication) and on various types of data (e.g., scalarfloating point, packed integer, packed floating point, vector integer,vector floating point). While some embodiments may include a number ofexecution units dedicated to specific functions or sets of functions,other embodiments may include only one execution unit or multipleexecution units that all perform all functions. The scheduler unit(s)956, physical register file(s) unit(s) 958, and execution cluster(s) 960are shown as being possibly plural because certain embodiments createseparate pipelines for certain types of data/operations (e.g., a scalarinteger pipeline, a scalar floating point/packed integer/packed floatingpoint/vector integer/vector floating point pipeline, and/or a memoryaccess pipeline that each have their own scheduler unit, physicalregister file(s) unit, and/or execution cluster—and in the case of aseparate memory access pipeline, certain embodiments are implemented inwhich only the execution cluster of this pipeline has the memory accessunit(s) 964). It should also be understood that where separate pipelinesare used, one or more of these pipelines may be out-of-orderissue/execution and the rest in-order.

The set of memory access units 964 is coupled to the memory unit 970,which includes a data TLB unit 972 coupled to a data cache unit 974coupled to a level 2 (L2) cache unit 976. In one exemplary embodiment,the memory access units 964 may include a load unit, a store addressunit, and a store data unit, each of which is coupled to the data TLBunit 972 in the memory unit 970. The instruction cache unit 934 isfurther coupled to a level 2 (L2) cache unit 976 in the memory unit 970.The L2 cache unit 976 is coupled to one or more other levels of cacheand eventually to a main memory.

By way of example, the exemplary register renaming, out-of-orderissue/execution core architecture may implement the pipeline 900 asfollows: 1) the instruction fetch 938 performs the fetch and lengthdecoding stages 902 and 904; 2) the decode unit 940 performs the decodestage 906; 3) the rename/allocator unit 952 performs the allocationstage 908 and renaming stage 910; 4) the scheduler unit(s) 956 performsthe schedule stage 912; 5) the physical register file(s) unit(s) 958 andthe memory unit 970 perform the register read/memory read stage 914; theexecution cluster 960 perform the execute stage 916; 6) the memory unit970 and the physical register file(s) unit(s) 958 perform the writeback/memory write stage 918; 7) various units may be involved in theexception handling stage 922; and 8) the retirement unit 954 and thephysical register file(s) unit(s) 958 perform the commit stage 924.

The core 990 may support one or more instructions sets (e.g., the x86instruction set (with some extensions that have been added with newerversions); the MIPS instruction set of MIPS Technologies of Sunnyvale,Calif.; the ARM instruction set (with optional additional extensionssuch as NEON) of ARM Holdings of Sunnyvale, Calif.), including theinstruction(s) described herein. In one embodiment, the core 990includes logic to support a packed data instruction set extension (e.g.,AVX1, AVX2, and/or some form of the generic vector friendly instructionformat (U=0 and/or U=1) previously described), thereby allowing theoperations used by many multimedia applications to be performed usingpacked data.

It should be understood that the core may support multithreading(executing two or more parallel sets of operations or threads), and maydo so in a variety of ways including time sliced multithreading,simultaneous multithreading (where a single physical core provides alogical core for each of the threads that physical core issimultaneously multithreading), or a combination thereof (e.g., timesliced fetching and decoding and simultaneous multithreading thereaftersuch as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-orderexecution, it should be understood that register renaming may be used inan in-order architecture. While the illustrated embodiment of theprocessor also includes separate instruction and data cache units934/974 and a shared L2 cache unit 976, alternative embodiments may havea single internal cache for both instructions and data, such as, forexample, a Level 1 (L1) internal cache, or multiple levels of internalcache. In some embodiments, the system may include a combination of aninternal cache and an external cache that is external to the core and/orthe processor. Alternatively, all of the cache may be external to thecore and/or the processor.

Specific Exemplary In-Order Core Architecture

FIGS. 10A-B illustrate a block diagram of a more specific exemplaryin-order core architecture, which core would be one of several logicblocks (including other cores of the same type and/or different types)in a chip. The logic blocks communicate through a high-bandwidthinterconnect network (e.g., a ring network) with some fixed functionlogic, memory I/O interfaces, and other necessary I/O logic, dependingon the application.

FIG. 10A is a block diagram of a single processor core, along with itsconnection to the on-die interconnect network 1002 and with its localsubset of the Level 2 (L2) cache 1004, according to embodiments of theinvention. In one embodiment, an instruction decoder 1000 supports thex86 instruction set with a packed data instruction set extension. An L1cache 1006 allows low-latency accesses to cache memory into the scalarand vector units. While in one embodiment (to simplify the design), ascalar unit 1008 and a vector unit 1010 use separate register sets(respectively, scalar registers 1012 and vector registers 1014) and datatransferred between them is written to memory and then read back in froma level 1 (L1) cache 1006, alternative embodiments of the invention mayuse a different approach (e.g., use a single register set or include acommunication path that allow data to be transferred between the tworegister files without being written and read back).

The local subset of the L2 cache 1004 is part of a global L2 cache thatis divided into separate local subsets, one per processor core. Eachprocessor core has a direct access path to its own local subset of theL2 cache 1004. Data read by a processor core is stored in its L2 cachesubset 1004 and can be accessed quickly, in parallel with otherprocessor cores accessing their own local L2 cache subsets. Data writtenby a processor core is stored in its own L2 cache subset 1004 and isflushed from other subsets, if necessary. The ring network ensurescoherency for shared data. The ring network is bi-directional to allowagents such as processor cores, L2 caches and other logic blocks tocommunicate with each other within the chip. Each ring data-path is1012-bits wide per direction.

FIG. 10B is an expanded view of part of the processor core in FIG. 10Aaccording to embodiments of the invention. FIG. 10B includes an L1 datacache 1006A part of the L1 cache 1004, as well as more detail regardingthe vector unit 1010 and the vector registers 1014. Specifically, thevector unit 1010 is a 16-wide vector processing unit (VPU) (see the16-wide ALU 1028), which executes one or more of integer,single-precision float, and double-precision float instructions. The VPUsupports swizzling the register inputs with swizzle unit 1020, numericconversion with numeric convert units 1022A-B, and replication withreplication unit 1024 on the memory input.

Processor with Integrated Memory Controller and Graphics

FIG. 11 is a block diagram of a processor 1100 that may have more thanone core, may have an integrated memory controller, and may haveintegrated graphics according to embodiments of the invention. The solidlined boxes in FIG. 11 illustrate a processor 1100 with a single core1102A, a system agent 1110, a set of one or more bus controller units1116, while the optional addition of the dashed lined boxes illustratesan alternative processor 1100 with multiple cores 1102A-N, a set of oneor more integrated memory controller unit(s) 1114 in the system agentunit 1110, and special purpose logic 1108.

Thus, different implementations of the processor 1100 may include: 1) aCPU with the special purpose logic 1108 being integrated graphics and/orscientific (throughput) logic (which may include one or more cores), andthe cores 1102A-N being one or more general purpose cores (e.g., generalpurpose in-order cores, general purpose out-of-order cores, acombination of the two); 2) a coprocessor with the cores 1102A-N being alarge number of special purpose cores intended primarily for graphicsand/or scientific (throughput); and 3) a coprocessor with the cores1102A-N being a large number of general purpose in-order or out-of-ordercores. Thus, the processor 1100 may be a general-purpose processor,coprocessor or special-purpose processor, such as, for example, anetwork or communication processor, compression engine, graphicsprocessor, GPGPU (general purpose graphics processing unit), ahigh-throughput many integrated core (MIC) coprocessor (including 30 ormore cores), embedded processor, or the like. The processor may beimplemented on one or more chips. The processor 1100 may be a part ofand/or may be implemented on one or more substrates using any of anumber of process technologies, such as, for example, BiCMOS, CMOS, orNMOS.

The memory hierarchy includes one or more levels of cache within thecores, a set or one or more shared cache units 1106, and external memory(not shown) coupled to the set of integrated memory controller units1114. The set of shared cache units 1106 may include one or moremid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), orother levels of cache, a last level cache (LLC), and/or combinationsthereof. While in one embodiment a ring based interconnect unit 1112interconnects the integrated graphics logic 1108, the set of sharedcache units 1106, and the system agent unit 1110/integrated memorycontroller unit(s) 1114, alternative embodiments may use any number ofwell-known techniques for interconnecting such units. In one embodiment,coherency is maintained between one or more cache units 1106 and cores1102-A-N.

In some embodiments, one or more of the cores 1102A-N are capable ofmultithreading. The system agent 1110 includes those componentscoordinating and operating cores 1102A-N. The system agent unit 1110 mayinclude for example a power control unit (PCU) and a display unit. ThePCU may be or include logic and components needed for regulating thepower state of the cores 1102A-N and the integrated graphics logic 1108.The display unit is for driving one or more externally connecteddisplays.

The cores 1102A-N may be homogenous or heterogeneous in terms ofarchitecture instruction set; that is, two or more of the cores 1102A-Nmay be capable of execution the same instruction set, while others maybe capable of executing only a subset of that instruction set or adifferent instruction set.

Exemplary Computer Architectures

FIGS. 12-15 are block diagrams of exemplary computer architectures.Other system designs and configurations known in the arts for laptops,desktops, handheld PCs, personal digital assistants, engineeringworkstations, servers, network devices, network hubs, switches, embeddedprocessors, digital signal processors (DSPs), graphics devices, videogame devices, set-top boxes, micro controllers, cell phones, portablemedia players, hand held devices, and various other electronic devices,are also suitable. In general, a huge variety of systems or electronicdevices capable of incorporating a processor and/or other executionlogic as disclosed herein are generally suitable.

Referring now to FIG. 12, shown is a block diagram of a system 1200 inaccordance with one embodiment of the present invention. The system 1200may include one or more processors 1210, 1215, which are coupled to acontroller hub 1220. In one embodiment the controller hub 1220 includesa graphics memory controller hub (GMCH) 1290 and an Input/Output Hub(IOH) 1250 (which may be on separate chips); the GMCH 1290 includesmemory and graphics controllers to which are coupled memory 1240 and acoprocessor 1245; the IOH 1250 is couples input/output (I/O) devices1260 to the GMCH 1290. Alternatively, one or both of the memory andgraphics controllers are integrated within the processor (as describedherein), the memory 1240 and the coprocessor 1245 are coupled directlyto the processor 1210, and the controller hub 1220 in a single chip withthe IOH 1250.

The optional nature of additional processors 1215 is denoted in FIG. 12with broken lines. Each processor 1210, 1215 may include one or more ofthe processing cores described herein and may be some version of theprocessor 1100.

The memory 1240 may be, for example, dynamic random access memory(DRAM), phase change memory (PCM), or a combination of the two. For atleast one embodiment, the controller hub 1220 communicates with theprocessor(s) 1210, 1215 via a multi-drop bus, such as a frontside bus(FSB), point-to-point interface such as QuickPath Interconnect (QPI), orsimilar connection 1295.

In one embodiment, the coprocessor 1245 is a special-purpose processor,such as, for example, a high-throughput MIC processor, a network orcommunication processor, compression engine, graphics processor, GPGPU,embedded processor, or the like. In one embodiment, controller hub 1220may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1210, 1215 in terms of a spectrum of metrics of merit includingarchitectural, microarchitectural, thermal, power consumptioncharacteristics, and the like.

In one embodiment, the processor 1210 executes instructions that controldata processing operations of a general type. Embedded within theinstructions may be coprocessor instructions. The processor 1210recognizes these coprocessor instructions as being of a type that shouldbe executed by the attached coprocessor 1245. Accordingly, the processor1210 issues these coprocessor instructions (or control signalsrepresenting coprocessor instructions) on a coprocessor bus or otherinterconnect, to coprocessor 1245. Coprocessor(s) 1245 accept andexecute the received coprocessor instructions.

Referring now to FIG. 13, shown is a block diagram of a first morespecific exemplary system 1300 in accordance with an embodiment of thepresent invention. As shown in FIG. 13, multiprocessor system 1300 is apoint-to-point interconnect system, and includes a first processor 1370and a second processor 1380 coupled via a point-to-point interconnect1350. Each of processors 1370 and 1380 may be some version of theprocessor 1100. In one embodiment of the invention, processors 1370 and1380 are respectively processors 1210 and 1215, while coprocessor 1338is coprocessor 1245. In another embodiment, processors 1370 and 1380 arerespectively processor 1210 coprocessor 1245.

Processors 1370 and 1380 are shown including integrated memorycontroller (IMC) units 1372 and 1382, respectively. Processor 1370 alsoincludes as part of its bus controller units point-to-point (P-P)interfaces 1376 and 1378; similarly, second processor 1380 includes P-Pinterfaces 1386 and 1388. Processors 1370, 1380 may exchange informationvia a point-to-point (P-P) interface 1350 using P-P interface circuits1378, 1388. As shown in FIG. 13, IMCs 1372 and 1382 couple theprocessors to respective memories, namely a memory 1332 and a memory1334, which may be portions of main memory locally attached to therespective processors.

Processors 1370, 1380 may each exchange information with a chipset 1390via individual P-P interfaces 1352, 1354 using point to point interfacecircuits 1376, 1394, 1386, 1398. Chipset 1390 may optionally exchangeinformation with the coprocessor 1338 via a high-performance interface1339. In one embodiment, the coprocessor 1338 is a special-purposeprocessor, such as, for example, a high-throughput MIC processor, anetwork or communication processor, compression engine, graphicsprocessor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor oroutside of both processors, yet connected with the processors via P-Pinterconnect, such that either or both processors' local cacheinformation may be stored in the shared cache if a processor is placedinto a low power mode.

Chipset 1390 may be coupled to a first bus 1316 via an interface 1396.In one embodiment, first bus 1316 may be a Peripheral ComponentInterconnect (PCI) bus, or a bus such as a PCI Express bus or anotherthird generation I/O interconnect bus, although the scope of the presentinvention is not so limited.

As shown in FIG. 13, various I/O devices 1314 may be coupled to firstbus 1316, along with a bus bridge 1318 which couples first bus 1316 to asecond bus 1320. In one embodiment, one or more additional processor(s)1315, such as coprocessors, high-throughput MIC processors, GPGPU's,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessor, are coupled to first bus 1316. In one embodiment, second bus1320 may be a low pin count (LPC) bus. Various devices may be coupled toa second bus 1320 including, for example, a keyboard and/or mouse 1322,communication devices 1327 and a storage unit 1328 such as a disk driveor other mass storage device which may include instructions/code anddata 1330, in one embodiment. Further, an audio I/O 1324 may be coupledto the second bus 1320. Note that other architectures are possible. Forexample, instead of the point-to-point architecture of FIG. 13, a systemmay implement a multi-drop bus or other such architecture.

Referring now to FIG. 14, shown is a block diagram of a second morespecific exemplary system 1400 in accordance with an embodiment of thepresent invention. Like elements in FIGS. 13 and 14 bear like referencenumerals, and certain aspects of FIG. 13 have been omitted from FIG. 14in order to avoid obscuring other aspects of FIG. 14.

FIG. 14 illustrates that the processors 1370, 1380 may includeintegrated memory and I/O control logic (“CL”) 1372 and 1382,respectively. Thus, the CL 1372, 1382 include integrated memorycontroller units and include I/O control logic. FIG. 14 illustrates thatnot only are the memories 1332, 1334 coupled to the CL 1372, 1382, butalso that I/O devices 1414 are also coupled to the control logic 1372,1382. Legacy I/O devices 1415 are coupled to the chipset 1390.

Referring now to FIG. 15, shown is a block diagram of a SoC 1500 inaccordance with an embodiment of the present invention. Similar elementsin FIG. 11 bear like reference numerals. Also, dashed lined boxes areoptional features on more advanced SoCs. In FIG. 15, an interconnectunit(s) 1502 is coupled to: an application processor 1510 which includesa set of one or more cores 202A-N and shared cache unit(s) 1106; asystem agent unit 1110; a bus controller unit(s) 1116; an integratedmemory controller unit(s) 1114; a set or one or more coprocessors 1520which may include integrated graphics logic, an image processor, anaudio processor, and a video processor; an static random access memory(SRAM) unit 1530; a direct memory access (DMA) unit 1532; and a displayunit 1540 for coupling to one or more external displays. In oneembodiment, the coprocessor(s) 1520 include a special-purpose processor,such as, for example, a network or communication processor, compressionengine, GPGPU, a high-throughput MIC processor, embedded processor, orthe like.

Embodiments of the mechanisms disclosed herein may be implemented inhardware, software, firmware, or a combination of such implementationapproaches. Embodiments of the invention may be implemented as computerprograms or program code executing on programmable systems comprising atleast one processor, a storage system (including volatile andnon-volatile memory and/or storage elements), at least one input device,and at least one output device.

Program code, such as code 1330 illustrated in FIG. 13, may be appliedto input instructions to perform the functions described herein andgenerate output information. The output information may be applied toone or more output devices, in known fashion. For purposes of thisapplication, a processing system includes any system that has aprocessor, such as, for example; a digital signal processor (DSP), amicrocontroller, an application specific integrated circuit (ASIC), or amicroprocessor.

The program code may be implemented in a high level procedural or objectoriented programming language to communicate with a processing system.The program code may also be implemented in assembly or machinelanguage, if desired. In fact, the mechanisms described herein are notlimited in scope to any particular programming language. In any case,the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented byrepresentative instructions stored on a machine-readable medium whichrepresents various logic within the processor, which when read by amachine causes the machine to fabricate logic to perform the techniquesdescribed herein. Such representations, known as “IP cores” may bestored on a tangible, machine readable medium and supplied to variouscustomers or manufacturing facilities to load into the fabricationmachines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation,non-transitory, tangible arrangements of articles manufactured or formedby a machine or device, including storage media such as hard disks, anyother type of disk including floppy disks, optical disks, compact diskread-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), andmagneto-optical disks, semiconductor devices such as read-only memories(ROMs), random access memories (RAMS) such as dynamic random accessmemories (DRAMs), static random access memories (SRAMs), erasableprogrammable read-only memories (EPROMs), flash memories, electricallyerasable programmable read-only memories (EEPROMs), phase change memory(PCM), magnetic or optical cards, or any other type of media suitablefor storing electronic instructions.

Accordingly, embodiments of the invention also include non-transitory,tangible machine-readable media containing instructions or containingdesign data, such as Hardware Description Language (HDL), which definesstructures, circuits, apparatuses, processors and/or system featuresdescribed herein. Such embodiments may also be referred to as programproducts.

Emulation (Including Binary Translation, Code Morphine, Etc.)

In some cases, an instruction converter may be used to convert aninstruction from a source instruction set to a target instruction set.For example, the instruction converter may translate (e.g., using staticbinary translation, dynamic binary translation including dynamiccompilation), morph, emulate, or otherwise convert an instruction to oneor more other instructions to be processed by the core. The instructionconverter may be implemented in software, hardware, firmware, or acombination thereof. The instruction converter may be on processor, offprocessor, or part on and part off processor.

FIG. 16 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the invention. In the illustrated embodiment, the instructionconverter is a software instruction converter, although alternativelythe instruction converter may be implemented in software, firmware,hardware, or various combinations thereof. FIG. 16 shows a program in ahigh level language 1602 may be compiled using an x86 compiler 1604 togenerate x86 binary code 1606 that may be natively executed by aprocessor with at least one x86 instruction set core 1616. The processorwith at least one x86 instruction set core 1616 represents any processorthat can perform substantially the same functions as an Intel processorwith at least one x86 instruction set core by compatibly executing orotherwise processing (1) a substantial portion of the instruction set ofthe Intel x86 instruction set core or (2) object code versions ofapplications or other software targeted to run on an Intel processorwith at least one x86 instruction set core, in order to achievesubstantially the same result as an Intel processor with at least onex86 instruction set core. The x86 compiler 1604 represents a compilerthat is operable to generate x86 binary code 1606 (e.g., object code)that can, with or without additional linkage processing, be executed onthe processor with at least one x86 instruction set core 1616.Similarly, FIG. 16 shows the program in the high level language 1602 maybe compiled using an alternative instruction set compiler 1608 togenerate alternative instruction set binary code 1610 that may benatively executed by a processor without at least one x86 instructionset core 1614 (e.g., a processor with cores that execute the MIPSinstruction set of MIPS Technologies of Sunnyvale, Calif. and/or thatexecute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.).The instruction converter 1612 is used to convert the x86 binary code1606 into code that may be natively executed by the processor without anx86 instruction set core 1614. This converted code is not likely to bethe same as the alternative instruction set binary code 1610 because aninstruction converter capable of this is difficult to make; however, theconverted code will accomplish the general operation and be made up ofinstructions from the alternative instruction set. Thus, the instructionconverter 1612 represents software, firmware, hardware, or a combinationthereof that, through emulation, simulation or any other process, allowsa processor or other electronic device that does not have an x86instruction set processor or core to execute the x86 binary code 1606.

What is claimed is:
 1. A system comprising: a plurality of cores toperform simultaneous multithreading, at least one of the cores toperform out-of-order instruction execution of instructions of aplurality of threads; at least one shared cache circuit to be sharedamong two or more of the cores; at least one of the cores comprising: aninstruction fetch circuit to fetch instructions of one or more of thethreads; an instruction decode circuit to decode the instructions; aregister renaming circuit to rename registers of a register file; aninstruction cache to store instructions to be executed; a data cache tostore data; at least one buffer to store entries associated with loadand store instructions; transaction processing circuitry to process atransactional region of instructions including one or more of the loadinstructions and store instructions associated with a firsttransactional region, the transaction processing circuitry to process atransaction begin instruction that indicates a start of thetransactional region of instructions and a transaction end instructionthat indicates an end of the transactional region of instructions; thetransaction processing circuitry to assign a transaction identifier todistinguish between transactional regions; transaction checkpointcircuitry to store an architectural state in response to the start ofthe transactional region of instructions; transaction status circuitryto store a programmable failure indication associated with a firsttransaction, wherein the first transaction to fail or proceed based onits associated failure indication, and wherein the programmable failureindication is to indicate failure in response to data loaded by thefirst transaction being modified by a second transaction; and circuitryto restore the architectural state stored by the transaction checkpointcircuitry in response to a failure of the first transaction; a memorycontroller to couple the cores to system memory; and at least one sharedcache to be shared among two or more the of cores.
 2. The system as inclaim 1 further comprising: an accelerator interface circuit to coupleone or more of the cores to an accelerator device.
 3. The system as inclaim 1 wherein the data cache includes at least one bit per cache linewhich is to be set when data is speculatively read from the cache lineby the transactional region, the at least one bit usable to identify thecache line as being utilized by the transactional region.
 4. The systemas in claim 3 wherein the at least one bit is to be cleared uponcompletion of the transactional region.
 5. The system as in claim 1further comprising a peripheral component interconnect express (PCIe)circuit.
 6. The system as in claim 1 further comprising: at least onestorage device coupled to one or more of the cores.
 7. The system as inclaim 1 further comprising: at least one communication device coupled toone or more of the cores.
 8. The system as in claim 1 wherein the systemmemory comprises a dynamic random access memory.
 9. The system as inclaim 1 further comprising: one or more accelerator devices coupled tothe accelerator interface circuit.
 10. The system as in claim 9 whereinthe one or more accelerator devices comprise field programmable gatearray (FPGA) devices.
 11. The system as in claim 1 further comprising: agraphics circuit to perform graphics processing operations.
 12. A systemcomprising: simultaneous multithreading means of a plurality of cores toperform out-of-order instruction execution of a plurality of threads;shared cache means to be shared among two or more of the cores; at leastone of the cores comprising: instruction fetch means to fetchinstructions of one or more of the threads; instruction decode means todecode the instructions; register renaming means to rename registers ofa register file; instruction cache means to store instructions to beexecuted; data cache means to store data; load/store buffer means tostore entries associated with load and store instructions; transactionprocessing means to process a transactional region of instructionsincluding one or more of the load instructions and store instructionsassociated with a first transactional region, the transaction processingmeans to process a transaction begin instruction that indicates a startof the transactional region of instructions and a transaction endinstruction that indicates an end of the transactional region ofinstructions; the transaction processing means to assign a transactionidentifier to distinguish between transactional regions; transactioncheckpoint means to store an architectural state in response to thestart of the transactional region of instructions; transaction statusmeans to store a programmable failure indication associated with a firsttransaction, wherein the first transaction to fail or proceed based onits associated failure indication, and wherein the programmable failureindication is to indicate failure in response to data loaded by thefirst transaction being modified by a second transaction; and restoremeans to restore the architectural state stored by the transactioncheckpoint circuitry in response to a failure of the first transaction;memory controller means to couple the cores to system memory; and sharedcache means to be shared among two or more the of cores.
 13. The systemas in claim 12 further comprising: accelerator interface means to coupleone or more of the cores to an accelerator device.
 14. The system as inclaim 12 wherein the data cache means includes at least one bit percache line which is to be set when data is speculatively read from thecache line by the transactional region, the at least one bit usable toidentify the cache line as being utilized by the transactional region.15. The system as in claim 14 wherein the at least one bit is to becleared upon completion of the transactional region.
 16. The system asin claim 12 further comprising storage means coupled to one or more ofthe cores.
 17. The system as in claim 12 further comprisingcommunication device means coupled to one or more of the cores.
 18. Thesystem as in claim 12 further comprising: accelerator means coupled tothe accelerator interface means.
 19. The system as in claim 18 whereinthe accelerator means comprises a field programmable gate array (FPGA)device.
 20. The system as in claim 12 further comprising: graphicsprocessing means to perform graphics processing operations.
 21. A methodcomprising: performing simultaneous multithreading of a plurality ofthreads and out-of-order execution of instructions of the plurality ofthreads on a plurality of cores; sharing a cache among two or more ofthe cores; fetching instructions of one or more of the threads; decodingthe instructions; renaming registers of a register file; storinginstructions to be executed in an instruction cache; storing data in adata cache; storing entries associated with load and store instructionsin a load/store buffer; processing a transactional region ofinstructions including one or more of the load instructions and storeinstructions associated with a first transactional region; processing atransaction begin instruction that indicates a start of thetransactional region of instructions and a transaction end instructionthat indicates an end of the transactional region of instructions;assigning a transaction identifier to distinguish between transactionalregions; storing an architectural state in response to the start of thetransactional region of instructions; storing a programmable failureindication associated with a first transaction, wherein the firsttransaction to fail or proceed based on its associated failureindication, and wherein the programmable failure indication is toindicate failure in response to data loaded by the first transactionbeing modified by a second transaction; and restoring the storedarchitectural state in response to a failure of the first transaction.coupling the cores to a system memory through a memory controller; andsharing a shared cache among two or more the of cores.
 21. The method asin claim 20 further comprising: coupling one or more of the cores to anaccelerator device.
 22. The method as in claim 20 wherein the data cacheincludes at least one bit per cache line which is to be set when data isspeculatively read from the cache line by the transactional region, theat least one bit usable to identify the cache line as being utilized bythe transactional region.
 23. The method as in claim 22 wherein the atleast one bit is to be cleared upon completion of the transactionalregion.
 24. The method as in claim 20 further comprising couplingstorage to one or more of the cores.
 25. The method as in claim 20further comprising coupling a communication device to one or more of thecores.